In conventional thermosetting type solder resist inks, curing accelerators, such as imidazoles, phosphonium salts and melamine-based compounds, have been used, as disclosed in Japanese Patent Laid-Open Publication No. 117922/2006 (patent document 1) and Japanese Patent Laid-Open Publication No. 298613/2005 (patent document 2). In recent years, improvement of low-temperature curability and instantaneous curability has been required for the solder resist inks because the heat-curing process has been shortened by the pursuit of cost down by the users or under the influences of relaxation of the heating conditions. In addition, tack-free property, low warpage property, electrical insulation property and a property that the solder resist inks do not contaminate a curing oven and the like to the last by outgassing due to heating have been also required.
The above compounds hitherto used, however, are insufficient in both of low-temperature curability and instantaneous curability, and tack-free property cannot be realized for shortage of cure. If the amount of the curing accelerator is increased for the purpose of improving them, enhancement of low-temperature curability, enhancement of instantaneous curability and tack-free property can be realized. However, because the curing reaction proceeds excessively, a pot life after blending of the components cannot be sufficiently ensured, resulting in a problem that the working life is shortened. Further, if the amount of the curing accelerator is increased, there are brought about a bad effect that low warpage property of a cured product cannot be ensured, a bad effect that the electrical insulation property is lowered by the excess curing accelerator and a bad effect that outgassing is caused by heating the excess curing accelerator and by the outgassing a curing oven and the like are contaminated.
The thermosetting type solder resist inks and the like are used for printed wiring boards, flexible printed wiring boards, chip-on-films (COF), etc. In the case of, for example, chip-on-films (COF), the number of pins of a chip such as IC or LSI is increased as the resolution of an image is heightened, and with increase of the number of pins, the distance between wirings of a substrate as a driver for driving tends to be decreased more and more. On this account, enhancement of reliability of electrical insulation between wirings has been demanded more than before. Chip-on-films (COF) having a pitch of 35 to 40 μm (total of wiring width and distance between wirings) have been mass-produced now, but introduction of design of 30 μm pitch or 25 μm pitch in future is planned, and enhancement of reliability of electrical insulation between wirings has become an essential problem.
The chip-on-films (COF) also play a role of joining an image plane of a liquid crystal or the like to a rigid printed wiring board for controlling the image plane. In the case where the chip-on-film (COF) is laminated onto them, the demand for low warpage property of the chip-on-film (COF) has become stronger and stronger in order to raise alignment accuracy. Also in the case where IC, LSI or the like is mounted on a substrate, alignment accuracy is important, and low warpage property has been likewise demanded.
In the production of chip-on-films (COF), a flexible base is stored in the form of a wound tape in order to efficiently carry out mass production, and with unwinding the flexible base, steps of wiring formation by etching, tin plating treatment, application and heat curing of a solder resist ink, quality inspection, etc. are carried out. If the surface of an insulating protective film has tackiness, unwinding of the tape becomes difficult in the step subsequent to the film formation step, specifically the quality inspection step, and this is disadvantageous in working. Further, a tape whose quality inspection has finished is also stored in such a state that the tape is wound around a reel, and the tape is shipped to the maker who mounts IC, LSI or the like on the tape. If the insulating protective film has tackiness, tapes adhere to each other during storage before shipment, and when the tape is unwound by the maker for mounting, disadvantages occur.
In the case of the chip-on-films (COF), tinplating is carried out on the wiring frequently. It is known that if the tin plating layer is exposed to a temperature of not lower than 130° C., tin undergoes migration in the depth direction of the copper wiring, and the tin plating layer becomes thin. In the case where a joining method in which a gold-tin eutectic crystal is formed between a gold plating layer provided on the terminal of IC, LSI or the like and a tin plating layer provided on the copper wiring is adopted in the mounting of IC, LSI or the like, the eutectic crystal is not sufficiently formed to thereby bring about joining failure when the tin plating layer is thin, and therefore, curing at 150° C. that is a curing temperature of a thermosetting resin used for usual solder resists cannot be carried out.
Patent document 1: Japanese Patent Laid-Open Publication No. 117922/2006
Patent document 2: Japanese Patent Laid-Open Publication No. 298613/2005